Hardware Interrupt:-
As i have already discussed that there are 6 interrupt pins in the microprocessor used as Hardware Interrrupts given below:
TRAP
RST7.5
RST6.5
RST5.5
INTR
INTA is not an interrupt. INTA is used by the Microprocessor for sending
the acknowledgement. TRAP has highest priority and RST7.5 has second highest priority and so on.
The Vector address of these interrupts are given below:
1.TRAP:-It is non maskable edge and level triggered interrupt. TRAP has the highest priority and vectores interrupt. Edge and level triggered means that the TRAP must go high and remain high until it is acknowledged. In case of sudden power failure, it executes a ISR and send the data from main memory to backup memory.
As we know that TRAP can not be masked but it can be delayed using HOLD signal.
This interrupt transfers the microprocessor's control to location 0024H.
How a TRAP interrupt may be masked???
TRAP interrupts can only be masked by reseting the microprocessor. There is no other way to mask it.
2.RST7.5:-It has the second highest priority. It is maskable and edge level triggered interrupt. The vector address of this interrupt is 003CH. Edge sensitive means input goes high and no need to maintain high state until it is recognized.
How It may be masked??
It can also be reset or masked by reseting microprocessor. It can also be resetted by DI instruction.
3.RST6.5 and RST5.5:-These are level triggered and maskable interrupts. When RST6.5 pin is at logic 1, INTE flip-flop is set. RST 6.5 has third highest priority and RST 5.5 has fourth highest priority.
It can be masked by giving DI and SIM instructions or by reseting microprocessor.
4.INTR:-It is level triggered and maskable interrupt. It has the lowest priority. It can be disabled by reseting the microprocessor or by DI and SIM instruction.
The following sequence of events occurs when INTR signal goes high:
1. The 8085 checks the status of INTR signal during execution of each instruction.
2. If INTR signal is high, then 8085 complete its current instruction and sends active low interrupt acknowledge signal, if the interrupt is enabled.
3.On receiving the instruction, the 8085 save the address of next instruction on stack and execute received instruction.
